2.5 D packaging and interconnect technology is a promising semiconductor packaging technology that provides costs and reliability savings over 3 D packaging technology. 2.5 D packaging technology allows the integration of homogenous and non-homogenous chips on an interposer for enhanced performance and miniaturization.
One potential reliability issue in 2.5 D semiconductor packages is the thermo-mechanical stress exerted on conductive interconnections bonded to the interposer. For example, in 2.5 D semiconductor packages that incorporate inorganic interposers (e.g., silicon interposers), a coefficient of thermal expansion (CTE) mismatch between the inorganic interposer and the organic substrate may stress the conductive interconnections (e.g., controlled collapse chip connection (C4) bumps) that bond the inorganic interposer to the substrate. Alternatively, in 2.5 D semiconductor packages that incorporate organic interposers, a CTE mismatch between the organic interposer and the inorganic semiconductor dies exert thermo-mechanical stress on the conductive interconnections (e.g., micro-bumps) that bond the semiconductor dies to the interposer. In any event, techniques for reducing thermo-mechanical stress exerted on the conductive interconnections bonding the interposer to the substrate/semiconductor-dies in 2.5 D packages are desired.
Another potential reliability and/or functional issue in 2.5 D semiconductor packages occurs when the laterally adjacent semiconductor dies have different heights. More specifically, the height differential may increase the likelihood that a taller chip will be nicked (or otherwise damaged) during manufacturing, as the taller chip may be susceptible to being struck when manufacturing processes (e.g., mounting, etc.) are performed on the shorter chip. Further, the height differential may inhibit functionality of the 2.5 D semiconductor chip. For example, the height differential may prevent the two chips from sharing a common heat sink. Accordingly, techniques for reducing height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages are desired.